1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of transmission lines that transmit data, and particular relates to a semiconductor device having a configuration in which electric charge stored in each of the transmission lines is reused.
2. Description of Related Art
Generally, in order to achieve lower power consumption in a semiconductor device such as DRAM, it is required to reduce charge/discharge current flowing when signals are transmitted through transmission lines such as a plurality of bit lines arranged in a memory cell array. Therefore, techniques for reducing the charge/discharge current by reusing electric charge stored in the transmission lines have been conventionally proposed. For example, Patent Reference 1 discloses a technique in which first and second common source lines for driving a sense amplifier of DRAM are short-circuited by a switch between both the common source lines so that electric charge of the first common source line that has been stored during a precedent sensing operation is reused for driving the second common source line during a subsequent sensing operation. For example, Patent References 2 and 3 disclose a charge reusing technique that can be applied to a refresh operation for memory cell arrays of the same type. For example, Patent Reference 4 discloses a charge reusing technique that can be utilized in randomly accessing the memory cell array. For example, Patent References 5 and 6 disclose a technique in which electric charge stored in parasitic capacitances of signal lines controlling the memory cell array is reused therebetween.    [Patent Reference 1] Japanese Patent Application Laid-open No. 5-135580 (U.S. Pat. No. 5,337,271)    [Patent Reference 2] Japanese Patent Application Laid-open No. 7-141877    [Patent Reference 3] Japanese Patent Application Laid-open No. 8-147969 (U.S. Pat. No. 5,694,445)    [Patent Reference 4] Japanese Patent Application Laid-open No. 8-249885    [Patent Reference 5] Japanese Patent Application Laid-open No. 10-149683    [Patent Reference 6] Japanese Patent Application Laid-open No. 2004-134058 (U.S. Pub. No. 2004-0052146)
However, a configuration having a memory cell array in which bit lines and sense amplifiers are hierarchized has been proposed with an increase in capacity of semiconductor memory devices such as DRAM. Generally, a hierarchical memory cell array is hierarchized into local bit lines of a lower hierarchy and global bit lines of an upper hierarchy, and thereby the number of memory cells connected to each local bit line can be suppressed so as to reduce influence of the parasitic capacitances and the like. In such a configuration, particularly when employing a single-ended structure for the bit line and the sense amplifier, it is required to reduce consumption current when data of each memory cell is inverted and readout through the local bit line and the global bit line and thereafter the data is re-inverted and restored to the memory cell by a global sense amplifier or the like.
However, the technique of the Patent Reference 1 is applied to a continuous refresh operation, and cannot be applied to reduce the consumption current when inverting and driving the data of the global bit line in the hierarchical memory cell array. The techniques of the Patent References 2, 3 and 4 have a problem of an increase in area for arranging a capacitor having a large capacitance that stores the electric charge to be reused or a large number of capacitors. The technique of the Patent Reference 5 is applied to an operation in which one signal line selected from a plurality of signal lines is selectively driven, and cannot be applied to reduce the consumption current when inverting and driving the data of the global bit line in the hierarchical memory cell array. The technique of the Patent Reference 6 is applied to an operation in which, when discharging electric charge of one signal line to be driven first, another signal line to be driven subsequently is charged, and cannot be applied to reduce the consumption current when inverting and driving the data of the global bit line in the hierarchical memory cell array. In this manner, according to charge reusing techniques applicable in the conventional semiconductor devices, methods effective for suppressing the consumption current in a restore operation in the hierarchical memory cell array have not been proposed yet.